Design and Implementation of Modified Sequential Parallel RNS Forward Converters

The Residue Number System (RNS) is suitable for DSP architectures because of its ability to perform fast carry-free arithmetic. However, this advantage is over-shadowed by the complexity involved in the conversion of numbers between binary to RNS representations and have prevented the widespread use of RNS. Converting a number from a binary representation to its RNS equivalent is known as forward conversion while the inverse operation is called reverse conversion. Even though reverse conversion is generally more complex, forward conversion for arbitrary modulo sets is not simpler. However, forward conversion for arbitrary modulo sets is memory intensive. There are three main approaches for forward conversion. The first approach involves pre-computing all possible values that the conversion requires and storing these values in memory. The second approach involves using efficient arithmetic units called combinational logic along with memory (LUT). In both cases, the memory size requirement increases as the dynamic range increases. The third approach is memory less in that it involves only combinatorial logic in the design. In this thesis we proposed to four different architectures for second approach which uses combinational logic along with memory (LUTs). The first architecture is purely sequential conversion in the second architecture is combination of sequential and parallel. The third architecture is the modified version of second architecture and fourth architecture is purely parallel. Forward converter architecture is designed and implemented to reduce the area, speed. Verilog HDL is used for coding and implementation of different architectures has been done on XILINX VERTEX 5XC5VLX110T-2FF1136 OPEN SPARC board. It is been identified that modified sequential /parallel approach has better performance in speed and area when compared with existing architectures.